文献类型：期刊文献

英文题名：FPGA implementation of region growing-global inhibition segmentation algorithm

作者：Liu, Jia[1,4]; Xu, Liqun[2,4]; Liu, Yuansheng[2,4]; Niu, Wenliang[3,4]

第一作者：Liu, Jia;刘佳

机构：[1] School of Computer Science and Engineering, Beihang University, Beijing, China; [2] College of Information Technology, Beijing Union University, Beijing, China; [3] College of Applied Science and Technology, Beijing Union University, China; [4] College of Information Technology, Key Laboratory of Information Service Engineering, Beijing Union University, China

第一机构：School of Computer Science and Engineering, Beihang University, Beijing, China

年份：2016

卷号：17

期号：30

起止页码：8.1-8.9

外文期刊名：International Journal of Simulation: Systems, Science and Technology

收录：EI(收录号：20164502992896);Scopus(收录号：2-s2.0-84994130869)

基金：This paper is supported by (Beijing Higher Education Young Elite Teacher Project) YETP1773. The paper is supported by open project of Beijing Key Laboratory of Information Service Engineering. This paper is supported by (Funding Project for Academic Human Resourses Development in Beijing Union University)Rx100201510. The paper is supported by CIT&TCD 201304074.

语种：英文

外文关键词：Computation theory - Computer vision - Field programmable gate arrays (FPGA) - Image processing - Integrated circuits - Logic programming - Object recognition - Pixels - Reconfigurable hardware

摘要：The image segmentation is an important foundation for machine mobile object recognition. With the constant development of machine vision application technology, all image segment methods are appeared. Meanwhile, machine vision application technology is developed towards the high-level integration. The paper has presented a region growing-overall suppressing segmentation algorithm. The main frame of image segmentation network structure is completely applicable to digital circuit and can realize the parallel processing of image pixel cell. Therefore, the computational logic structure is proposed for this algorithm and FPGA is implemented according to the logic structure to obtain simulation result. The simulation result shows the calculated FPGA implementation realizes the target of image segmentation. The parallel computation can be implemented among pixel cells. Compared with the traditional image segmentation algorithm, it can greatly reduce the computation time. The computation FPGA provides theoretical and technical preparations for future real-time image process and a new method for the implementation of machine mobile object recognition. ? 2016, UK Simulation Society. All rights reserved.