文献类型：会议论文

英文题名：NoC architecture study with DFG model

作者：Jia, Liu[1]; Li, Zheying[1]; Li, Shuo[2]

第一作者：刘佳

通讯作者：Jia, L.

机构：[1] Institute of Micro Electronic Application Technology, Beijing Union University, Beijing, China; [2] Dept. of Microelectronics and Information Technology, Royal Institute of Technology [KTH], Stockholm, Sweden

第一机构：北京联合大学智慧城市学院

会议论文集：Proceedings - 2010 1st International Conference on Pervasive Computing, Signal Processing and Applications, PCSPA 2010

会议日期：17 September 2010 through 19 September 2010

会议地点：Harbin

语种：英文

外文关键词：Data flow analysis - Data flow graphs - Data transfer - Mapping - Network architecture - Network-on-chip - Programmable logic controllers - Routers - Signal processing - System-on-chip - Ubiquitous computing

摘要：Generic reconfigurable network on chip (GRNoC) is an advanced technology of application specified SoC design for digital signal process system (DSPS). A novel GRNoC mapping method based on data flow graph (DFG) is addressed in this paper. For modules of heterogeneous processors, central memory, and IPs (intellectual properties), DFG model analysis shows that DFG model provides important data transmission properties included the direction and contents of data transmitting, requirements of synchronization and speed of data transmission. The DFG model combined with graph model of GRNoC, therefore, can be the base of route mapping design for the GRNoC. In addition, node architecture of simple router used in GRNoC is also proposed in this paper. The simple router can increases the properties of data transmission in GRNoC and is more suitable for mapping design with DFG model. ? 2010 IEEE.