文献类型：期刊文献

中文题名：JTAG指令处理器IP软核设计

英文题名：The IP Soft Core Design of JTAG Instruction Processor

作者：董承[1];何朝军[1];吕彩霞[2]

第一作者：董承

机构：[1]北京交通大学电子信息工程学院,北京100044;[2]北京联合大学信息学院,北京100101

第一机构：北京交通大学电子信息工程学院,北京100044

年份：2011

期号：5

起止页码：55-60

中文期刊名：中国电子商情：通信市场

语种：中文

中文关键词：JTAG技术;TAP控制器;VerilogHDL

外文关键词：SoC, IP core, task flow, USB protocol controller

摘要：边界扫描技术是一种应用于数字集成电路器件的标准化可测试性设计方法，它提供了对电路板上元件的功能、互连及相互间影响进行测试的一种新方案，极大地方便了系统电路的浏试。自从1990年2月JTAG与IEEE标准化委员会合作提出了“标准测试访问通道与边界扫描结构”的IEEE1149．1．1990标准以后，边界扫描技术得到了迅速发展和应用。JTAG指令处理器是边界扫描电路的核心部件，在对TAP控制器的仿真验证同时，讨论JTAG相关指令与边界扫描测试方式。
This article raised a digit circuit IP soft core verification based on task flow. According to the design requirement of digit circuit IP soft core, it categorizes the original IP core and divides a complicated verification task into different sub-tasks according to the functions the IP core can achieve. Then it conducts verification of different sub-tasks and connects them into a specific soft core task aim and thus forms a task flow. This article chooses a part of complicated IP soft core for verification, divides into different tasks according to its functional structure and sets up a comprehensive task implementation model. Finally, from the verification result of Modelsim tool, we can see that the IP core verification that based on task flow can accurately categorize IP modules so as to avoid leaving out functions and verify all functions oflP cores.