文献类型：会议论文

英文题名：A Low Power Architecture Design Method Based on DFG Model

作者：Chen, Tingting[1];Li, Zheying[1]

第一作者：陈婷婷

通讯作者：Chen, TT[1]

机构：[1]Beijing Union Univ, Coll Informat, Beijing, Peoples R China

第一机构：北京联合大学智慧城市学院

通讯机构：[1]corresponding author), Beijing Union Univ, Coll Informat, Beijing, Peoples R China.|[1141734]北京联合大学智慧城市学院;[11417]北京联合大学;

会议论文集：5th IEEE Conference on Industrial Electronics and Applications

会议日期：JUN 15-17, 2010

会议地点：Taichung, TAIWAN

语种：英文

外文关键词：logic model; DFG model; time characteristic; low power architecture design

摘要：A low power architecture design method is brought forward by this paper based on DFG (Data Flow Graphic) model. Through this method, a DFG model is extracted from the logic model of a circuit or a system and is used to optimize the circuit architecture for reducing the power consumption of circuit. In this paper, the data transmission process of USB2.0 is taken as an example to prove the correctness of this low power architecture design method.