文献类型：会议论文

英文题名：Architecture Design of a Comparator for SAR ADC

作者：Xiu Limei[1];Li Zheying[1]

第一作者：修丽梅

通讯作者：Xiu, LM[1]

机构：[1]Beijing Union Univ, Inst Microelect Applicat Tech, Beijing 100101, Peoples R China

第一机构：北京联合大学智慧城市学院

通讯机构：[1]corresponding author), Beijing Union Univ, Inst Microelect Applicat Tech, Beijing 100101, Peoples R China.|[1141734]北京联合大学智慧城市学院;[11417]北京联合大学;

会议论文集：8th International Symposium on Test Measure

会议日期：AUG 23-26, 2009

会议地点：Chongqing, PEOPLES R CHINA

语种：英文

外文关键词：High-precision; low power dissipation; Switched Operational Amplifier

摘要：A novel high-speed and high-precision voltage comparator has been proposed. In the comparator design, the Switched Operational Amplifier technique is adopted in the pre-amplifier stage to reduce the power consumption. The proposed voltage comparator is designed for 1MHz 12-bit SAR ADC under TSMC 180nm 1P6M CMOS technology. The resolution of the voltage comparator is 0.2mV under the 1.8V power supply with the sample rate of 20MS/s.