文献类型：会议论文

英文题名：NoC design with DFG model for DSPS

作者：Zheying, Li[1]; Jia, Liu[1]; Shuo, Li[2]

第一作者：Zheying, Li

通讯作者：Zheying, L.

机构：[1] Institute of Micro Electronic Application Technology, Beijing Union University, Beijing, China; [2] Dept. of Microelectronics and Information Technology, Royal Institute of Technology [KTH], Stockholm, Sweden

第一机构：北京联合大学智慧城市学院

会议论文集：Proceedings - International Conference on Electrical and Control Engineering, ICECE 2010

会议日期：26 June 2010 through 28 June 2010

会议地点：Wuhan

语种：英文

外文关键词：Data flow analysis - Data flow graphs - Data transfer - Mapping - Network-on-chip - Programmable logic controllers - Routers - Signal processing - System-on-chip

摘要：The mapping design of network on chip (NoC) is one of the cores of SoC design for digital signal process system (DSPS). A NoC mapping method based on data flow graph (DFG) is addressed in this paper. For modules of heterogeneous processors, central memory, and IPs (intellectual properties), DFG model analysis shows that DFG model provides important data transmission properties included the direction and contents of data transmitting, requirements of synchronization and speed of data transmission. The DFG model, therefore, can be the base of route mapping design for the NoC. In addition, node architecture of simple router used in generic regulable NoC (GRNoC) is also proposed in this paper. The simple router can increases the properties of data transmission in NoC and is more suitable for mapping design with DFG model. ? 2010 IEEE.