文献类型：会议论文

英文题名：Improved power scaling issue for pipeline ADC

作者：Chen, Tingting[1];Li, Zheying[1];Li, Bo[2];Li, Yuemei[2];Wang, Chunlei[2];Wang, Jianjian[2]

第一作者：陈婷婷

通讯作者：Chen, TT[1]

机构：[1]Beijing Union Univ, Informat Sch, Beijing 100101, Peoples R China;[2]Jiao Tong Univ, Sch Elect Engn, Beijing 100044, Peoples R China

第一机构：北京联合大学智慧城市学院

通讯机构：[1]corresponding author), Beijing Union Univ, Informat Sch, Beijing 100101, Peoples R China.|[1141734]北京联合大学智慧城市学院;[11417]北京联合大学;

会议论文集：International Symposium on Intelligent Signal Processing and Communication Systems

会议日期：NOV 28-DEC 01, 2007

会议地点：Xiamen, PEOPLES R CHINA

语种：英文

外文关键词：pipeline ADC; power scaling; comparator; sample and hold amplifier

摘要：In this paper an improved method to design a power optimized pipeline ADC is presented. By analyzing the architecture of SHA and the dependency of power on SNI?, supply voltage and sampling rate, the flowchart instructing the design of pipeline ADC is put forward which simultaneously determines the resolution distribution, the optimum value for capacitors scaling factor, the parameter of OTA in each stage. A 0.18-mu m 10-bit 80-MS/s CMOS prototype achieves 58.1dB SNDR is implemented to validate the power scaling approach.