文献类型：会议论文

英文题名：Research on Instruction Pipeline Optimization Oriented to RISC-V Vector Instruction Set

作者：Zhang, Zhen[1]; Yu, Xin[2]

第一作者：Zhang, Zhen

机构：[1] Beijing Key Laboratory of Information Service Engineering, Beijing Union University, Beijing, 100101, China; [2] College of Urban Rail Transit and Logistics, Beijing Union University, Beijing, 100101, China

第一机构：北京联合大学北京市信息服务工程重点实验室

会议论文集：Advances in Artificial Intelligence and Security - 8th International Conference on Artificial Intelligence and Security, ICAIS 2022, Proceedings

会议日期：July 15, 2022 - July 20, 2022

会议地点：Qinghai, China

语种：英文

外文关键词：Deep learning - General purpose computers - Parallel processing systems - Pipeline processing systems - Pipelines - Reduced instruction set computing

摘要：Traditional general-purpose processors are scalar processors, and only one data result is obtained when an instruction is executed. But nowadays, there are a lot of data parallel computing operations in deep learning algorithms. At this time, it is particularly important to improve the parallelism of data so as to improve the performance of operations. SIMD technology can significantly improve parallelism. As an open source simplified instruction set architecture, RISC-V has released a stable SIMD instruction set version. On these foundations, this article will explore the optimization of data parallelism on the XT-910 chip based on the RISC-V architecture of PingtouGe Semiconductor, and conduct instruction pipeline optimization research to fit its pipeline architecture, reduce latency, and improve instruction throughput. The experimental results show that after using the instruction pipeline optimization method, the performance of the memory copy algorithm on the RISC-V platform under different data scales is improved by 1.52 times compared with that before the optimization. ? 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.